1. Field of the Invention
The present invention relates to a semiconductor device formed by mesa etching and a manufacturing method thereof.
2. Description of the Background Art
For field-effect transistors such as MESFETs (Metal Semiconductor Field-Effect Transistors) using compound semiconductors such as GaAs, various kinds of self-aligned processes are developed to reduce the effect of the surface depletion layer to reduce the source resistance. When manufacturing such a field-effect transistor, certain layers are formed on a GaAs substrate by MBE (Molecular-Beam Epitaxy), for example. Then a mesa etching process is applied to the epitaxial growth substrate for the purpose of device isolation.
FIG. 7 is a plan roughly showing an MESFET and FIGS. 8A to 8G are process sections showing a conventional MESFET manufacturing method. FIG. 9A is a plan mainly showing the photoresist pattern in mesa etching, and FIG. 9B is a plan showing the mesa pattern after the mesa etching.
As shown in FIG. 7, a gate electrode 11 is formed on an n-type doped layer 2 and a source electrode 9 and a drain electrode 10 are disposed on either side of the gate electrode 11. In FIG. 7, the direction parallel to the elongate direction (the gate width direction) of the gate electrode 11 is represented as a direction A and the direction perpendicular to the elongate direction of the gate electrode 11 is represented as a direction B.
In FIGS. 8A-8G, process sections seen in the direction A are shown on the left side and process sections seen in the direction B are shown on the right side. In this manufacturing method, a self-aligned process utilizing a reverse dummy-gate pattern is conducted by using a GaAs epitaxial growth substrate.
As shown in FIG. 8A, an n-type doped layer 2 is formed in the surface of a semi-insulating GaAs substrate 1. A 50-nm-thick SiN protection film 3 is formed by ECR-plasma-CVD (Electron Cyclotron Resonance Plasma Chemical Vapor Deposition) on the n-type doped layer 2, and a dummy gate 4 is formed on the SiN protection film 3 with photoresist. Then n.sup.+ -type doped layers (high-concentration doped regions) 5a, 5b for obtaining ohmic contact are formed in the surface of the GaAs substrate 1 by a self-aligned ion implantation by using the dummy gate 4 as a mask.
Next, as shown in FIG. 8B, the dummy gate 4 is etched by oxygen plasma to reduce the dummy gate length. Thus the dummy gate length is reduced from W1 to W2.
Next, as shown in FIG. 8C, an SiO.sub.2 film 6 is formed all over the SiN protection film 3 and the dummy gate 4 by ECR-plasma-CVD. Subsequently, the SiO.sub.2 film 6 is selectively etched only in the part attached on the sidewall of the dummy gate 4 with buffered hydrofluoric acid composed of a mixed solution containing HF and NH.sub.4 F in a ratio of 1:100.
Further, as shown in FIG. 8D, the dummy gate 4 is removed together with the SiO.sub.2 film 6 thereon by lift-off to reverse the pattern of the dummy gate 4. A reverse dummy-gate pattern 60 composed of the SiO.sub.2 film 6 is thus formed. Then, to activate the n.sup.+ -type doped layers 5a, 5b, annealing is applied for a short time with a halogen lamp.
Next, as shown in FIG. 8E, a photoresist pattern 7 is formed on the reverse dummy-gate pattern 60 and the SiN protection film 3 therebetween (refer to FIG. 9A), and the exposed part of the SiN protection film 3 is etched by using the reverse dummy-gate pattern 60 and the photoresist pattern 7 as masks. Then mesa etching is applied for device isolation with a mixed solution of tartaric acid and hydrogen peroxide. The mesa pattern 8 is thus formed (refer to FIG. 9B).
Next, as shown in FIG. 8F, the photoresist pattern 7 for mesa etching is removed and then a source electrode 9 and a drain electrode 10 of AuGe/Ni/Au are formed respectively on the n.sup.+ -type doped layers 5a, 5b by using patterning technology, and a gate electrode 11 of Ti/Pd/Au is formed on the n-type doped layer 2.
Finally, as shown in FIG. 8G, a protection film 12 for moisture resistance is formed all over the surface and contact holes are formed in the protection film 12 above the source electrode 9 and the drain electrode 10, and then electrodes 13, 14 for connection with an external bias power-supply are formed by patterning technology.
As shown in FIG. 9B, the length W3 of the side of the mesa pattern 8 in the gate width direction (the direction A) corresponds to the gate width of the MESFET. The length in the gate width direction of the n.sup.+ -type doped layers 5a, 5b located under the reverse dummy-gate pattern 60 is equal to or longer than the gate width.
In the above-described conventional MESFET manufacturing method, in the mesa etching step shown in FIG. 8E, the SiN protection film 3 forms a protrusion like an awning over the periphery of the mesa pattern 8.
When the protection film 12 is formed for moisture resistance in the process step shown in FIG. 8G, this protrusion forms a small gap D in the protection film 12 on the stepped part between the mesa pattern 8 and the SiN protection film 3 (the mesa-step portion), as shown in FIG. 10A. Moisture resistance tests show that water penetrates through the gap D to the contact between the gate electrode 11 and the GaAs substrate 1, as shown by the arrows X, Y in FIG. 10B, to deteriorate characteristics of the MESFET.